/* * libbinrec: a recompiling translator for machine code * Copyright (c) 2016 Andrew Church * * This software may be copied and redistributed under certain conditions; * see the file "COPYING" in the source code distribution for details. * NO WARRANTY is provided with this software. */ #include "tests/guest-ppc/insn/common.h" static const uint8_t input[] = { 0xFC,0x40,0x18,0x90, // fmr f2,f3 0x10,0x20,0x10,0x90, // ps_mr f1,f2 }; static const unsigned int guest_opt = 0; static const unsigned int common_opt = 0; static const bool expected_success = true; static const char expected[] = "[info] Scanning terminated at requested limit 0x7\n" " 0: LOAD_ARG r1, 0\n" " 1: LOAD_ARG r2, 1\n" " 2: GET_ALIAS r3, a4\n" " 3: FGETSTATE r4\n" " 4: GET_ALIAS r5, a3\n" " 5: VINSERT r6, r5, r3, 0\n" " 6: VFCMP r7, r6, r6, UN\n" " 7: VFCVT r8, r6\n" " 8: SET_ALIAS a5, r8\n" " 9: GOTO_IF_Z r7, L1\n" " 10: VEXTRACT r9, r6, 0\n" " 11: VEXTRACT r10, r6, 1\n" " 12: BFEXT r11, r7, 0, 32\n" " 13: BFEXT r12, r7, 32, 32\n" " 14: ZCAST r13, r11\n" " 15: ZCAST r14, r12\n" " 16: BITCAST r15, r9\n" " 17: BITCAST r16, r10\n" " 18: NOT r17, r15\n" " 19: NOT r18, r16\n" " 20: LOAD_IMM r19, 0x8000000000000\n" " 21: AND r20, r17, r19\n" " 22: AND r21, r18, r19\n" " 23: VEXTRACT r22, r8, 0\n" " 24: VEXTRACT r23, r8, 1\n" " 25: SRLI r24, r20, 29\n" " 26: SRLI r25, r21, 29\n" " 27: ZCAST r26, r24\n" " 28: ZCAST r27, r25\n" " 29: BITCAST r28, r22\n" " 30: BITCAST r29, r23\n" " 31: AND r30, r26, r13\n" " 32: AND r31, r27, r14\n" " 33: XOR r32, r28, r30\n" " 34: XOR r33, r29, r31\n" " 35: BITCAST r34, r32\n" " 36: BITCAST r35, r33\n" " 37: VBUILD2 r36, r34, r35\n" " 38: SET_ALIAS a5, r36\n" " 39: LABEL L1\n" " 40: GET_ALIAS r37, a5\n" " 41: FSETSTATE r4\n" " 42: FGETSTATE r38\n" " 43: VFCMP r39, r37, r37, UN\n" " 44: VFCVT r40, r37\n" " 45: SET_ALIAS a6, r40\n" " 46: GOTO_IF_Z r39, L2\n" " 47: VEXTRACT r41, r37, 0\n" " 48: VEXTRACT r42, r37, 1\n" " 49: SLLI r43, r39, 32\n" " 50: BITCAST r44, r41\n" " 51: BITCAST r45, r42\n" " 52: NOT r46, r44\n" " 53: NOT r47, r45\n" " 54: ANDI r48, r46, 4194304\n" " 55: ANDI r49, r47, 4194304\n" " 56: VEXTRACT r50, r40, 0\n" " 57: VEXTRACT r51, r40, 1\n" " 58: ZCAST r52, r48\n" " 59: ZCAST r53, r49\n" " 60: SLLI r54, r52, 29\n" " 61: SLLI r55, r53, 29\n" " 62: BITCAST r56, r50\n" " 63: BITCAST r57, r51\n" " 64: AND r58, r54, r43\n" " 65: AND r59, r55, r39\n" " 66: XOR r60, r56, r58\n" " 67: XOR r61, r57, r59\n" " 68: BITCAST r62, r60\n" " 69: BITCAST r63, r61\n" " 70: VBUILD2 r64, r62, r63\n" " 71: SET_ALIAS a6, r64\n" " 72: LABEL L2\n" " 73: GET_ALIAS r65, a6\n" " 74: FSETSTATE r38\n" " 75: SET_ALIAS a2, r65\n" " 76: GET_ALIAS r66, a3\n" " 77: VINSERT r67, r66, r3, 0\n" " 78: SET_ALIAS a3, r67\n" " 79: LOAD_IMM r68, 8\n" " 80: SET_ALIAS a1, r68\n" " 81: RETURN r1\n" "\n" "Alias 1: int32 @ 964(r1)\n" "Alias 2: float64[2] @ 400(r1)\n" "Alias 3: float64[2] @ 416(r1)\n" "Alias 4: float64 @ 432(r1)\n" "Alias 5: float32[2], no bound storage\n" "Alias 6: float64[2], no bound storage\n" "\n" "Block 0: --> [0,9] --> 1,2\n" "Block 1: 0 --> [10,38] --> 2\n" "Block 2: 1,0 --> [39,46] --> 3,4\n" "Block 3: 2 --> [47,71] --> 4\n" "Block 4: 3,2 --> [72,81] --> \n" ; #include "tests/rtl-disasm-test.i"