/* * libbinrec: a recompiling translator for machine code * Copyright (c) 2016 Andrew Church * * This software may be copied and redistributed under certain conditions; * see the file "COPYING" in the source code distribution for details. * NO WARRANTY is provided with this software. */ #include "tests/guest-ppc/insn/common.h" #define ADD_READONLY_REGION static const uint8_t input[] = { 0x94,0x21,0xFF,0xF0, // stwu r1,-16(r1) 0x3C,0x00,0x43,0x30, // lis r0,0x4330 0x90,0x01,0x00,0x08, // stw r0,8(r1) 0x90,0x61,0x00,0x0C, // stw r3,12(r1) 0xC8,0x41,0x00,0x08, // lfd f2,8(r1) 0x3C,0x60,0x00,0x00, // lis r3,0 0xC8,0x63,0x00,0x28, // lfd f3,const(r3) 0xFC,0x22,0x18,0x28, // fsub f1,f2,f3 0x38,0x21,0x00,0x10, // addi r1,r1,16 0x4E,0x80,0x00,0x20, // blr 0x43,0x30,0x00,0x00, // const: .int64 0x4330000000000000 0x00,0x00,0x00,0x00, }; static const unsigned int guest_opt = BINREC_OPT_G_PPC_DETECT_FCFI_EMUL; static const unsigned int common_opt = 0; static const bool expected_success = true; static const char expected[] = #ifdef RTL_DEBUG_OPTIMIZE "[info] Killing instruction 7\n" #endif " 0: LOAD_ARG r1, 0\n" " 1: LOAD_ARG r2, 1\n" " 2: GET_ALIAS r3, a3\n" " 3: ADDI r4, r3, -16\n" " 4: ZCAST r5, r4\n" " 5: ADD r6, r2, r5\n" " 6: STORE_BR 0(r6), r3\n" " 7: NOP\n" " 8: LOAD_IMM r7, 0x43300000\n" " 9: SET_ALIAS a2, r7\n" " 10: ZCAST r8, r4\n" " 11: ADD r9, r2, r8\n" " 12: STORE_BR 8(r9), r7\n" " 13: ZCAST r10, r4\n" " 14: ADD r11, r2, r10\n" " 15: GET_ALIAS r12, a4\n" " 16: STORE_BR 12(r11), r12\n" " 17: ZCAST r13, r4\n" " 18: ADD r14, r2, r13\n" " 19: LOAD_BR r15, 8(r14)\n" " 20: LOAD_IMM r16, 0\n" " 21: SET_ALIAS a4, r16\n" " 22: ZCAST r17, r16\n" " 23: ADD r18, r2, r17\n" " 24: LOAD_BR r19, 40(r18)\n" " 25: FZCAST r20, r12\n" " 26: BITCAST r21, r20\n" " 27: SGTUI r22, r21, 0\n" " 28: SLTSI r23, r21, 0\n" " 29: BFEXT r27, r21, 52, 11\n" " 30: SEQI r24, r27, 0\n" " 31: SEQI r25, r27, 2047\n" " 32: SLLI r28, r21, 12\n" " 33: SEQI r26, r28, 0\n" " 34: AND r29, r24, r26\n" " 35: XORI r30, r26, 1\n" " 36: AND r31, r25, r30\n" " 37: AND r32, r24, r22\n" " 38: OR r33, r32, r31\n" " 39: OR r34, r29, r31\n" " 40: XORI r35, r34, 1\n" " 41: XORI r36, r23, 1\n" " 42: AND r37, r23, r35\n" " 43: AND r38, r36, r35\n" " 44: SLLI r39, r33, 4\n" " 45: SLLI r40, r37, 3\n" " 46: SLLI r41, r38, 2\n" " 47: SLLI r42, r29, 1\n" " 48: OR r43, r39, r40\n" " 49: OR r44, r41, r42\n" " 50: OR r45, r43, r25\n" " 51: OR r46, r45, r44\n" " 52: GET_ALIAS r47, a9\n" " 53: BFINS r48, r47, r46, 12, 7\n" " 54: SET_ALIAS a9, r48\n" " 55: ADDI r49, r4, 16\n" " 56: SET_ALIAS a3, r49\n" " 57: SET_ALIAS a5, r20\n" " 58: SET_ALIAS a6, r15\n" " 59: SET_ALIAS a7, r19\n" " 60: GET_ALIAS r50, a8\n" " 61: ANDI r51, r50, -4\n" " 62: SET_ALIAS a1, r51\n" " 63: GOTO L1\n" " 64: LOAD_IMM r52, 40\n" " 65: SET_ALIAS a1, r52\n" " 66: LABEL L1\n" " 67: RETURN r1\n" "\n" "Alias 1: int32 @ 964(r1)\n" "Alias 2: int32 @ 256(r1)\n" "Alias 3: int32 @ 260(r1)\n" "Alias 4: int32 @ 268(r1)\n" "Alias 5: float64 @ 400(r1)\n" "Alias 6: float64 @ 416(r1)\n" "Alias 7: float64 @ 432(r1)\n" "Alias 8: int32 @ 932(r1)\n" "Alias 9: int32 @ 944(r1)\n" "\n" "Block 0: --> [0,63] --> 2\n" "Block 1: --> [64,65] --> 2\n" "Block 2: 1,0 --> [66,67] --> \n"; #include "tests/rtl-disasm-test.i"