/* * libbinrec: a recompiling translator for machine code * Copyright (c) 2016 Andrew Church * * This software may be copied and redistributed under certain conditions; * see the file "COPYING" in the source code distribution for details. * NO WARRANTY is provided with this software. */ #include "tests/guest-ppc/insn/common.h" static const uint8_t input[] = { 0xE0,0x23,0x0F,0xF0, // psq_l f1,-16(r3),0,0 0xF0,0x23,0x0F,0xF8, // psq_st f1,-8(r3),0,0 }; static const unsigned int guest_opt = BINREC_OPT_G_PPC_FORWARD_LOADS | BINREC_OPT_G_PPC_ASSUME_NO_SNAN; static const unsigned int common_opt = 0; static const bool expected_success = true; static const char expected[] = "[info] Scanning terminated at requested limit 0x7\n" " 0: LOAD_ARG r1, 0\n" " 1: LOAD_ARG r2, 1\n" " 2: GET_ALIAS r3, a2\n" " 3: ZCAST r4, r3\n" " 4: ADD r5, r2, r4\n" " 5: LOAD r6, 896(r1)\n" " 6: BFEXT r7, r6, 16, 3\n" " 7: ANDI r8, r7, 4\n" " 8: GOTO_IF_NZ r8, L2\n" /* The translator should not attempt to save the raw doubleword if not * assuming a constant GQR value. */ " 9: LOAD_BR r9, -16(r5)\n" " 10: LOAD_BR r10, -12(r5)\n" " 11: VBUILD2 r11, r9, r10\n" " 12: VFCVT r12, r11\n" " 13: SET_ALIAS a3, r12\n" " 14: GOTO L1\n" " 15: LABEL L2\n" " 16: SLLI r13, r6, 2\n" " 17: SRAI r14, r13, 26\n" " 18: SLLI r15, r14, 23\n" " 19: LOAD_IMM r16, 0x3F800000\n" " 20: SUB r17, r16, r15\n" " 21: BITCAST r18, r17\n" " 22: ANDI r19, r7, 1\n" " 23: GOTO_IF_NZ r19, L3\n" " 24: ANDI r20, r7, 2\n" " 25: GOTO_IF_NZ r20, L4\n" " 26: LOAD_U8 r21, -16(r5)\n" " 27: LOAD_U8 r22, -15(r5)\n" " 28: FSCAST r23, r21\n" " 29: FMUL r24, r23, r18\n" " 30: FSCAST r25, r22\n" " 31: FMUL r26, r25, r18\n" " 32: VBUILD2 r27, r24, r26\n" " 33: VFCVT r28, r27\n" " 34: SET_ALIAS a3, r28\n" " 35: GOTO L1\n" " 36: LABEL L4\n" " 37: LOAD_S8 r29, -16(r5)\n" " 38: LOAD_S8 r30, -15(r5)\n" " 39: FSCAST r31, r29\n" " 40: FMUL r32, r31, r18\n" " 41: FSCAST r33, r30\n" " 42: FMUL r34, r33, r18\n" " 43: VBUILD2 r35, r32, r34\n" " 44: VFCVT r36, r35\n" " 45: SET_ALIAS a3, r36\n" " 46: GOTO L1\n" " 47: LABEL L3\n" " 48: ANDI r37, r7, 2\n" " 49: GOTO_IF_NZ r37, L5\n" " 50: LOAD_U16_BR r38, -16(r5)\n" " 51: LOAD_U16_BR r39, -14(r5)\n" " 52: FSCAST r40, r38\n" " 53: FMUL r41, r40, r18\n" " 54: FSCAST r42, r39\n" " 55: FMUL r43, r42, r18\n" " 56: VBUILD2 r44, r41, r43\n" " 57: VFCVT r45, r44\n" " 58: SET_ALIAS a3, r45\n" " 59: GOTO L1\n" " 60: LABEL L5\n" " 61: LOAD_S16_BR r46, -16(r5)\n" " 62: LOAD_S16_BR r47, -14(r5)\n" " 63: FSCAST r48, r46\n" " 64: FMUL r49, r48, r18\n" " 65: FSCAST r50, r47\n" " 66: FMUL r51, r50, r18\n" " 67: VBUILD2 r52, r49, r51\n" " 68: VFCVT r53, r52\n" " 69: SET_ALIAS a3, r53\n" " 70: LABEL L1\n" " 71: GET_ALIAS r54, a3\n" " 72: ZCAST r55, r3\n" " 73: ADD r56, r2, r55\n" " 74: LOAD r57, 896(r1)\n" " 75: BFEXT r58, r57, 0, 3\n" " 76: ANDI r59, r58, 4\n" " 77: GOTO_IF_NZ r59, L7\n" " 78: VEXTRACT r60, r54, 0\n" " 79: BITCAST r61, r60\n" " 80: SRLI r62, r61, 32\n" " 81: ZCAST r63, r62\n" " 82: SLLI r64, r61, 1\n" " 83: GOTO_IF_Z r64, L8\n" " 84: LOAD_IMM r65, 0x701FFFFFFFFFFFFF\n" " 85: SGTU r66, r64, r65\n" " 86: GOTO_IF_Z r66, L9\n" " 87: LABEL L8\n" " 88: ANDI r67, r63, -1073741824\n" " 89: BFEXT r68, r61, 29, 30\n" " 90: ZCAST r69, r68\n" " 91: OR r70, r67, r69\n" " 92: STORE_BR -8(r56), r70\n" " 93: GOTO L10\n" " 94: LABEL L9\n" " 95: ANDI r71, r67, -2147483648\n" " 96: STORE_BR -8(r56), r71\n" " 97: LABEL L10\n" " 98: VEXTRACT r72, r54, 1\n" " 99: BITCAST r73, r72\n" " 100: SRLI r74, r73, 32\n" " 101: ZCAST r75, r74\n" " 102: SLLI r76, r73, 1\n" " 103: GOTO_IF_Z r76, L11\n" " 104: LOAD_IMM r77, 0x701FFFFFFFFFFFFF\n" " 105: SGTU r78, r76, r77\n" " 106: GOTO_IF_Z r78, L12\n" " 107: LABEL L11\n" " 108: ANDI r79, r75, -1073741824\n" " 109: BFEXT r80, r73, 29, 30\n" " 110: ZCAST r81, r80\n" " 111: OR r82, r79, r81\n" " 112: STORE_BR -4(r56), r82\n" " 113: GOTO L13\n" " 114: LABEL L12\n" " 115: ANDI r83, r79, -2147483648\n" " 116: STORE_BR -4(r56), r83\n" " 117: LABEL L13\n" " 118: GOTO L6\n" " 119: LABEL L7\n" " 120: SLLI r84, r57, 18\n" " 121: SRAI r85, r84, 26\n" " 122: SLLI r86, r85, 23\n" " 123: ADDI r87, r86, 1065353216\n" " 124: BITCAST r88, r87\n" " 125: ANDI r89, r58, 2\n" " 126: SLLI r90, r89, 14\n" " 127: ANDI r91, r58, 1\n" " 128: XORI r92, r91, 1\n" " 129: SLLI r93, r92, 3\n" " 130: LOAD_IMM r94, 0\n" " 131: LOAD_IMM r95, 65535\n" " 132: SUB r96, r94, r90\n" " 133: SUB r97, r95, r90\n" " 134: SRA r98, r96, r93\n" " 135: SRA r99, r97, r93\n" " 136: FGETSTATE r100\n" " 137: VFCVT r101, r54\n" " 138: VEXTRACT r102, r101, 0\n" " 139: FMUL r103, r102, r88\n" " 140: BITCAST r104, r103\n" " 141: FTRUNCI r105, r103\n" " 142: SLLI r106, r104, 1\n" " 143: SRLI r107, r104, 31\n" " 144: SELECT r108, r98, r99, r107\n" " 145: SGTUI r109, r106, -1895825409\n" " 146: SELECT r110, r108, r105, r109\n" " 147: SGTS r111, r110, r99\n" " 148: SELECT r112, r99, r110, r111\n" " 149: SLTS r113, r110, r98\n" " 150: SELECT r114, r98, r112, r113\n" " 151: VEXTRACT r115, r101, 1\n" " 152: FMUL r116, r115, r88\n" " 153: BITCAST r117, r116\n" " 154: FTRUNCI r118, r116\n" " 155: SLLI r119, r117, 1\n" " 156: SRLI r120, r117, 31\n" " 157: SELECT r121, r98, r99, r120\n" " 158: SGTUI r122, r119, -1895825409\n" " 159: SELECT r123, r121, r118, r122\n" " 160: SGTS r124, r123, r99\n" " 161: SELECT r125, r99, r123, r124\n" " 162: SLTS r126, r123, r98\n" " 163: SELECT r127, r98, r125, r126\n" " 164: FSETSTATE r100\n" " 165: ANDI r128, r58, 1\n" " 166: GOTO_IF_NZ r128, L14\n" " 167: STORE_I8 -8(r56), r114\n" " 168: STORE_I8 -7(r56), r127\n" " 169: GOTO L6\n" " 170: LABEL L14\n" " 171: STORE_I16_BR -8(r56), r114\n" " 172: STORE_I16_BR -6(r56), r127\n" " 173: LABEL L6\n" " 174: LOAD_IMM r129, 8\n" " 175: SET_ALIAS a1, r129\n" " 176: RETURN r1\n" "\n" "Alias 1: int32 @ 964(r1)\n" "Alias 2: int32 @ 268(r1)\n" "Alias 3: float64[2] @ 400(r1)\n" "\n" "Block 0: --> [0,8] --> 1,2\n" "Block 1: 0 --> [9,14] --> 9\n" "Block 2: 0 --> [15,23] --> 3,6\n" "Block 3: 2 --> [24,25] --> 4,5\n" "Block 4: 3 --> [26,35] --> 9\n" "Block 5: 3 --> [36,46] --> 9\n" "Block 6: 2 --> [47,49] --> 7,8\n" "Block 7: 6 --> [50,59] --> 9\n" "Block 8: 6 --> [60,69] --> 9\n" "Block 9: 8,1,4,5,7 --> [70,77] --> 10,19\n" "Block 10: 9 --> [78,83] --> 11,12\n" "Block 11: 10 --> [84,86] --> 12,13\n" "Block 12: 11,10 --> [87,93] --> 14\n" "Block 13: 11 --> [94,96] --> 14\n" "Block 14: 13,12 --> [97,103] --> 15,16\n" "Block 15: 14 --> [104,106] --> 16,17\n" "Block 16: 15,14 --> [107,113] --> 18\n" "Block 17: 15 --> [114,116] --> 18\n" "Block 18: 17,16 --> [117,118] --> 22\n" "Block 19: 9 --> [119,166] --> 20,21\n" "Block 20: 19 --> [167,169] --> 22\n" "Block 21: 19 --> [170,172] --> 22\n" "Block 22: 21,18,20 --> [173,176] --> \n" ; #include "tests/rtl-disasm-test.i"